Integrated circuits are formed on semiconductor wafers, which are then sawed into semiconductor chips. The semiconductor chips are then bonded onto package substrates. FIGS. 1 through 3 illustrate cross-sectional views of intermediate stages in a conventional bonding process. Referring to FIG. 1, package substrate 100 is provided, and bond pads 108 are at the surface of package substrate 100. Chip 102 is picked up and flipped over, with solder bumps 104 at a surface of chip 102 facing down. Flux 106 is also applied on solder bumps 104.
Next, as shown in FIG. 2, chip 102 is placed on package substrate 100, with solder bumps 104 being placed against bond pads 108. Package substrate 100 and chip 102 then go through a reflow process, during which package substrate 100 and chip 102, and solder bumps 104 are heated. The resulting bonded structure is shown in FIG. 3. Due to the weight of chip 102 and solder bumps 104, solder bumps 104, when melted, are collapsed, and width W1 of solder bumps 104 increases.
One of the problems found in the conventional bond structures is that cracking often occurs in solder bumps 104 after the bonding process, particularly near wherein solder bumps 104 join solder resists 112 and passivation layer (or polyimide layer) 114. In addition, due to the increase in width W1 of solder bumps 104, the spacing between neighboring solder bumps 104 decreases, causing greater risk of shorting bumps 104 to each other.